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Low-Power Design for Reconfigurable Computing

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If you have a question about this talk, please contact Dr George A Constantinides .

In this talk, we will focus on the sources of power consumption in modern reconfigurable logic devices (FPGAs) implementing numerical algorithms. The requirement for early-stage power estimation models for arithmetic circuits will be developed, and the challenges involved will be discussed. Some results from our research indicating the accuracy achievable at various levels of abstraction will be presented. We will close with one suggested use for high-level power models: allowing the automatic optimal tradeoff of power consumption for arithmetic roundoff error.

This talk is part of the CAS FPGA Talks series.

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