University of Cambridge > Talks.cam > Computer Laboratory Computer Architecture Group Meeting > Shorter Cycles, Better Chips: Compiler Infrastructure for Accelerating the Hardware-Software Design Loop

Shorter Cycles, Better Chips: Compiler Infrastructure for Accelerating the Hardware-Software Design Loop

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If you have a question about this talk, please contact Tobias Grosser .

As compute systems become increasingly heterogeneous and specialized, compiler infrastructure is no longer just a way to generate code—it can be a practical tool to shape hardware design decisions, tighten end-to-end design cycles, and share the verification burden.

From the perspective of a silicon startup building custom acceleration, this talk highlights opportunities that emerge when we treat compilation as a cross-cutting system: using compiler-driven feedback to connect RTL and architectural choices to the software stack and real workloads early enough to matter.

We will discuss how this broader view enables faster iteration through tighter hardware–software feedback loops, and how lowering workload descriptions into kernels, schedules, and data movement strategies can better exploit heterogeneous hardware.

Finally, we touch on how compiler-driven infrastructure can turn workloads and generated programs into systematic test vehicles—helping expose corner cases and improving confidence in correctness as both hardware and software evolve.

Bio: Moritz Scherer is the CTO of Mosaic SoC AG, where he leads the development of ultra-low-power embedded AI and computer vision hardware and the associated hardware–software stack, targeting AR/VR, robotics, and always-on edge intelligence.

He earned his PhD at ETH Z ürich in Luca Benini’s group, focusing on embedded heterogeneous acceleration and compiler toolchains for efficient deployment on resource-constrained systems. His work centers on full-stack co-design, bridging workload descriptions to efficient execution on specialized compute platforms.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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