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Towards architectural emulators for multiprocessors: PPCMEM2 status

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  • UserPeter Sewell
  • ClockWednesday 22 October 2014, 13:00-14:00
  • HouseFW11.

If you have a question about this talk, please contact Peter Sewell .

I’ll briefly summarise the status of our work towards an architectural emulator for multiprocessors with relaxed memory models, integrating an instruction semantics derived from the IBM Power vendor specification with an extension of our previous operational concurrency model.

In this talk I’ll focus mostly on some interesting questions about the interface between the instruction semantics and the concurrency model; some of these raise new questions about what the architectural specification should be.

This is work by Kathryn Gray, Stephen Kell, Gabriel Kerneis, Dominic Mulligan, Christopher Pulte, Susmit Sarkar, and Peter Sewell.

This talk is part of the REMS lunch series.

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FW 11, William Gates Building. Zoom link: https://cl-cam-ac-uk.zoom.us/j/4361570789?pwd=Nkl2T3ZLaTZwRm05bzRTOUUxY3Q4QT09&from=addon in person & via zoom Senior Common Room, POLIS, First Floor, 17 Mill Lane, Cambridge, CB2 1RX

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