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SUMMARY:Directed Speculation in Multi-core Memory Systems to Improve Perfo
 rmance and Efficiency - Dr. Paul V. Gratz
DTSTART:20180424T130000Z
DTEND:20180424T140000Z
UID:TALK103267@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:The scaling of multi-core processors poses a challenge to memo
 ry\nsystem design.  While process technology scaling provides greater\nnum
 bers of cores on each chip\, the transistor performance and power\ngains t
 hat traditionally accompanied process scaling have largely\nceased.  Scali
 ng performance with increased core counts must be\nachieved under the same
  or reduced energy and power budgets.\nFurthermore\, increased cores gener
 ate more accesses to shared caches\ncausing conflict misses as unrelated p
 rocesses compete for the same\ncache sets.  Each miss represents significa
 nt waste: wasted time as\nthe requested data is transferred from a slow ma
 in memory\, wasted\nenergy and bandwidth when transferring cache block wor
 ds that will\nultimately go unused.  In this talk I will explore the means
  to\nleverage memory locality speculation to reduce waste and improve\neff
 iciency in multi-core processor memory systems.  In particular\, I\nwill s
 how how control flow and effective address speculation can be\nused in a n
 ovel prefetch engine that improves IPC by 39%\,\noutperforming the best co
 mpeting design with only 1/3 the hardware state\noverhead. I will also dem
 onstrate a technique to extend this approach\nto speculate beyond memory s
 ynchronization semantics in multi-threaded\nworkloads.\n\nBIO: \n\nPaul V.
  Gratz is an Associate Professor in the department of\nElectrical and Comp
 uter Engineering at Texas A&M University\, currently\nvisiting the Univers
 ity of Edinburgh on sabbatical.  His research\ninterests include efficient
  and reliable design in the context of high\nperformance computer architec
 ture\, processor memory systems and\non-chip interconnection networks.  He
  received his B.S.  and\nM.S. degrees in Electrical Engineering from The U
 niversity of Florida\nin 1994 and 1997 respectively.  From 1997 to 2002 he
  was a design\nengineer with Intel Corporation.  He received his Ph.D. deg
 ree in\nElectrical and Computer Engineering from the University of Texas a
 t\nAustin in 2008.  His papers "Path Confidence based Lookahead\nPrefetchi
 ng" and "B-Fetch: Branch Prediction Directed Prefetching for\nChip-Multipr
 ocessors" were nominated for best papers at MICRO '16 and\nMICRO '14 respe
 ctively.  At ASPLOS '09\, Dr. Gratz received a best\npaper award for "An E
 valuation of the TRIPS Computer System."  In 2016\nhe received the "Distin
 guished Achievement Award in Teaching - College\nLevel" from the Texas A&M
  Association of Former Students and in 2017\nhe received the "Excellence A
 ward in Teaching\, 2017" from the Texas\nA&M College of Engineering.
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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