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SUMMARY:Programmable Logic Core Based Post-Silicon Debug For SoCs - Steve 
 Wilton\, Associate Professor\, University of British Columbia
DTSTART:20080213T110000Z
DTEND:20080213T120000Z
UID:TALK10756@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:Producing a functionally correct integrated circuit\nis becomi
 ng increasingly difficult. No matter how\ncareful a designer is\, there wi
 ll always be integrated\ncircuits that are fabricated\, but do not operate
  as\nexpected. Providing a means to effectively debug these\nintegrated ci
 rcuits is vital to help pin-point problems\nand reduce the number of re-sp
 ins required to create a\ncorrectly-functioning chip. In this talk\, I wil
 l show that\nprogrammable logic cores (PLCs) and flexible\nnetworks can pr
 ovide this debugging capability. I\nwill elaborate on our PLC based debug 
 infrastructure and\nsummarize our current research. I will address issues\
 nsuch as defining the debug architecture and debug\nmethodology\, determin
 ing the expected area overhead\,\noptimizing the interconnect topology\, c
 reating a high\nthroughput multi-frequency on-chip network and\nbuilding e
 fficient interfaces between the PLC and\nfixed-function logic.  Finally\, 
 I will give some insight into\nour latest work that combines our debug arc
 hitecture with\nformal verification techniques.\n
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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