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SUMMARY:Understanding PCIe performance for end host networking - Rolf Neug
 ebauer (Netronome)
DTSTART:20180816T143000Z
DTEND:20180816T150000Z
UID:TALK108622@talks.cam.ac.uk
CONTACT:Marco Caballero
DESCRIPTION:Abstract: This is a practice talk for ACM SIGCOMM 2018. In rec
 ent years\, spurred on by the development and availability of programmable
  NICs\, end hosts have increasingly become the enforcement point for core 
 network functions such as load balancing\, congestion control\, and applic
 ation specific network offloads. However\, implementing custom designs on 
 programmable NICs is not easy: many potential bottlenecks can impact perfo
 rmance. This paper focuses on the performance implication of PCIe\, the de
 -facto I/O interconnect in contemporary servers\, when interacting with th
 e host architecture and device drivers. We present a theoretical model for
  PCIe and pcie-bench\, an open-source suite\, that allows developers to ga
 in an accurate and deep understanding of the PCIe substrate. Using pcie-be
 nch\, we characterize the PCIe subsystem in modern servers. We highlight s
 urprising differences in PCIe implementations\, evaluate the undesirable i
 mpact of PCIe features such as IOMMUs\, and show the practical limits for 
 common network cards operating at 40Gb/s and beyond. Furthermore\, through
  pcie-bench we gained insights which guided software and future hardware a
 rchitectures for both commercial and research oriented network cards and D
 MA engines\n\n
LOCATION:LT2\, Computer Laboratory\, William Gates Building
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