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SUMMARY:Combining Scratch-Pad Placement with Loop Parallelisation for FPGA
 s - George Constantinides
DTSTART:20080611T151500Z
DTEND:20080611T161500Z
UID:TALK12424@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:I will discuss some joint work with my PhD student\, Qiang Liu
 \, on how to combine loop parallelisation with custom memory subsystem des
 ign\, targeting FPGA-based computation. We will show that the dependence b
 etween the two problems can be exposed and optimized over using a form of 
 constrained optimization called “Geometric Programming”. I will try to
  find time to begin the talk with an overview of convex optimization techn
 iques in general\, and geometric programming in particular\, in the hope t
 hat some of you may find an application for similar techniques in your own
  work.
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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