BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Talks.cam//talks.cam.ac.uk//
X-WR-CALNAME:Talks.cam
BEGIN:VEVENT
SUMMARY:Investigating I/O &amp\; Memory Bandwidth trade-offs for Iterative
  Algorithms’ - David Boland\, Imperial College London
DTSTART:20080703T110000Z
DTEND:20080703T120000Z
UID:TALK12750@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:Previous FPGA implementations of iterative algorithms\, such a
 s the conjugate gradient and minimum residual algorithm\, have focused eit
 her on maximum performance or maximum scalability. The designs for maximum
  performance have been based upon fully utilizing the memory bandwidth on 
 an FPGA\, however as the available memory is limited\, such a scheme is on
 ly possible for small matrix orders. The designs for maximum scalability u
 se external RAM to store the matrices and intermediate results\, however t
 his means the input data speed is determined by the I/O bandwidth and resu
 lts in a dramatically lower performance. This presentation analyses theore
 tically how it would be possible to trade these factors to achieve an opti
 mum performance for any given matrix order\, and briefly examines ways in 
 which to improve the results.
LOCATION:Mahanakorn Laboratory\, EEE
END:VEVENT
END:VCALENDAR