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SUMMARY:Memory and Datapath optimisation for FPGA co-processors - Kieron T
 urkington (Imperial College London)
DTSTART:20080814T130000Z
DTEND:20080814T140000Z
UID:TALK12756@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:The available memory bandwidth often forms the bottleneck in p
 erformance when using FPGAs as hardware co-processors. As a result\, when 
 considering high level synthesis for FPGAs\, it is important to optimise t
 he datapath and the supporting memory subsystem in parallel so that perfor
 mance can be maximised. This talk presents an overview for such a co-optim
 isation process\, based around loop pipelining\, and its application to a 
 sample benchmark.
LOCATION:Mahanakorn Laboratory\, EEE
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