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SUMMARY:An FPGA-based Implementation of the MINRES Algorithm - David Bolan
 d\, Imperial College London
DTSTART:20080805T103000Z
DTEND:20080805T111500Z
UID:TALK12801@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:Due to continuous improvements in the resources available on F
 PGAs\, it is becoming increasingly possible to accelerate floating point a
 lgorithms. The solution of a system of linear equations forms the basis of
  many problems in engineering and science\, but its calculation is highly 
 time consuming. The minimum residual algorithm (MINRES) is one method to s
 olve this problem\, and is highly effective provided the matrix exhibits c
 ertain characteristics. This paper examines\nan IEEE 754 single precision 
 floating point implementation of the MINRES algorithm on an FPGA. It demon
 strates that through parallelisation and heavy pipelining of all floating 
 point components it is possible to achieve a sustained performance of up t
 o 53 GFLOPS on the Virtex5-330T. This compares favourably to other hardwar
 e implementations of floating point matrix inversion algorithms\, and corr
 esponds to an improvement of nearly an order of magnitude compared to a so
 ftware implementation.
LOCATION:Mahanakorn Laboratory\, EEE
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