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SUMMARY:Combining Data Reuse Exploitation with Data-Level Parallelization 
 for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework 
 - Qiang Liu\, Imperial College London
DTSTART:20080805T111500Z
DTEND:20080805T120000Z
UID:TALK12802@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:A geometric programming framework is proposed in this paper to
  automate exploration of the design space consisting of data reuse (buffer
 ing) exploitation and loop-level parallelization\, in the context of FPGA-
 targeted hardware compilation. We expose the dependence between data reuse
  and data-level parallelization and explore both problems under the on-chi
 p memory constraint for performance-optimal designs within a single optimi
 zation step. Results from applying this framework to several real benchmar
 ks demonstrate that given different constraints on on-chip memory utilizat
 ion\, the corresponding performance-optimal designs are automatically dete
 rmined by the framework\, and performance improvements up to 4.7 times hav
 e been achieved compared with the method that first explores data reuse an
 d then performs parallelization.
LOCATION:Mahanakorn Laboratory\, EEE
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