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SUMMARY:CG: Optimizing FPGA Speed using Custom Precision - Antonio Roldao 
 (PhD@IC)
DTSTART:20081119T140000Z
DTEND:20081119T150000Z
UID:TALK14059@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:With the continuing exploration of accelerating iterative meth
 ods on FPGAs\, in this upcoming seminar\, I will present the latest result
 s obtained from analyzing the speed-up of an FPGA vs a CPU (in double prec
 ision) by reducing the word-length.  \n\nI will also show a plot of the di
 fferent number of iterations obtained from performing every sum reduction 
 (of the CG method) sequentially or in a tree\, for the current MPC Citatio
 n Model Aircraft testbench. \n\nIn addition\, I will show and request feed
 back on a preliminary poster on for the banded implementation paper that i
 s to be presented at FPT’08.
LOCATION:Mahanakorn Laboratory\, EEE
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