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SUMMARY:Wirelength Modeling for Homogeneous and Heterogeneous FPGA Archite
 ctural Development - Alastair Smith (Imperial College London)
DTSTART:20081020T110000Z
DTEND:20081020T120000Z
UID:TALK14144@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:This talk will detail the work that I undertook during my post
 -doctoral fellowship at The University of British Columbia. During my time
  there I was involved in developing models that describe FPGA architecture
 s. This talk will detail these models and how they can be used to predict 
 wirelength requirements\, both in terms of the circuits mapped to FPGAs an
 d how this in turn affects the requirements of the FPGA architecture.
LOCATION:Mahanakorn Laboratory\, EEE
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