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SUMMARY:Improving Real-time Observability in Embedded Logic Analysis - Nic
 ola Nicolici (McMaster University\, Canada)
DTSTART:20081107T160000Z
DTEND:20081107T170000Z
UID:TALK15133@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:To identify design errors that escape pre-silicon verification
 \, post-silicon validation is becoming an important step in the implementa
 tion flow of digital integrated circuits and systems. Embedded logic analy
 sis has emerged as a complementary technique to scan chains for improving 
 real-time observability during in-system validation. In this talk we discu
 ss some recent research for improving real-time observability in embedded 
 logic analysis.
LOCATION:Room 611\, EEE
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