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SUMMARY:(FPT Preview) Co-optimisation of Datapath and Memory in Outer Loop
  Pipelining - Kieron Turkington (Imperial College London)
DTSTART:20081128T110000Z
DTEND:20081128T120000Z
UID:TALK15398@talks.cam.ac.uk
CONTACT:Alastair Smith
DESCRIPTION:When targeting algorithms to FPGA based systems\nboth the arra
 y to memory assignment and the selection of data\nreuse structures must of
 ten be considered to maximise performance.\nIn this work we present an Int
 eger Linear Programming\nformulation for the combined problem of array to 
 memory\nassignment and data reuse selection. We include a number of\ncost 
 functions to minimise during memory optimisation and show\nhow these optim
 isations can be integrated into a loop pipelining\nframework to iterativel
 y update the memory subsystem during\nscheduling. By co-optimising the dat
 apath (schedule) and memory\nsubsystem we are able to produce near optimal
  (fastest)\nsolutions\, with an upper bound on the distance from the optim
 al\nsolution. Our results show an average speedup of up to 4x over\na non-
 optimised memory subsystem when integrated into an\nexisting outer loop pi
 pelining framework.\n\n
LOCATION:Mahanakorn Laboratory\, EEE
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