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SUMMARY:(FPT Preview) Modelling and Compensating for Clock Skew  Variabili
 ty in FPGAs - Dr Pete Sedcole (Imperial College London)
DTSTART:20081128T153000Z
DTEND:20081128T160000Z
UID:TALK15456@talks.cam.ac.uk
CONTACT:Alastair Smith
DESCRIPTION:Abstract not available
LOCATION:Mahanakorn Laboratory\, EEE
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