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SUMMARY:Improving Cache Performance while Mitigating Software Side-Channel
  Attacks - Ruby Lee - Princeton University
DTSTART:20090127T161500Z
DTEND:20090127T171500Z
UID:TALK16338@talks.cam.ac.uk
CONTACT:Joseph Bonneau
DESCRIPTION:Improving the security of computers has traditionally been ass
 ociated with degrading performance.  Princeton researchers show a rather s
 urprising result where both security and performance can be improved by re
 thinking cache architecture.  Cache subsystems bridge the speed gap betwee
 n processors and main memory\, and are essential for improving the perform
 ance of computer systems.  However\, the fundamental difference in cache h
 it versus miss timing can be exploited to leak secret information\, such a
 s the cryptographic keys of AES and RSA ciphers.  Almost all computers are
  vulnerable to these software side-channel attacks.  Software solutions ar
 e algorithm-specific\, do not apply to legacy programs and severely degrad
 e performance.  A generic hardware solution that applies to all software\,
  does not degrade performance\, and prevents all access-based cache side-c
 hannel attacks\, is desirable. New security-aware cache architectures\, pr
 esented in ISCA2007\, were the Random Permutation cache (RPcache) and the 
 Partition Locked cache (PLcache).  A novel cache architecture (Micro2008) 
 is presented that not only improves security\, but also improves performan
 ce\, achieving the best cache access time\, miss-rate and power consumptio
 n of existing classes of cache architectures.  Fault-tolerance\, hot-spot 
 mitigation and flexible partitioning are additional benefits. \n
LOCATION:Lecture Theatre 2\, Computer Laboratory\, William Gates Building
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