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SUMMARY:Enhancing Verilog - Cherif Salama (Rice University)
DTSTART:20090330T140000Z
DTEND:20090330T150000Z
UID:TALK17597@talks.cam.ac.uk
CONTACT:Boris Feigin
DESCRIPTION:Mainstream Hardware Description Languages (HDL) have not signi
 ficantly improved since their introduction despite the continuous increase
  in the size and complexity of circuits being designed. As a result hardwa
 re design has become harder and harder. Our work is a step toward alleviat
 ing this problem by enhancing the Verilog Hardware Description Language. S
 tatic synthesizability and wire consistency checking for circuit families 
 is one area where a large room for improvement is available.\n\nCircuit fa
 milies can be concisely described using existing Verilog's generative cons
 tructs (parameterized modules\, loops\, and conditionals).  These construc
 ts are eliminated during the elaboration phase and replaced by simpler Ver
 ilog code. By treating Verilog as a statically typed two-level language an
 d using indexed types\, we can formalize the elaboration phase while provi
 ding static guarantees on the properties of the generated circuits. This f
 ormalization allows us to statically detect: 1) Non Synthesizable circuits
 \, 2) Wire width mismatches\, 3) Array bounds violations\, and 4) Unreacha
 ble code. It also allows us to statically provide bounded parametric estim
 ates of the number of gates required to realize a particular circuit.\n
LOCATION:FW26\, Computer Laboratory
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