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SUMMARY:From Verification to Synthesis - Moshe Y. Vardi - Rice University
DTSTART:20090709T130000Z
DTEND:20090709T140000Z
UID:TALK19076@talks.cam.ac.uk
CONTACT:Microsoft Research Cambridge Talks Admins
DESCRIPTION:*Abstract:* One of the most significant developments in the ar
 ea of design verification over the last decade is the development of algor
 ithmic methods for verifying temporal specification of finite-state design
 s. A frequent criticism against this approach\, however\, is that verifica
 tion is done after significant resources have already been invested in the
  development of the design. Since designs invariably contains errors\, ver
 ification simply becomes part of the debugging process. The critics argue 
 that the desired goal is to use the specification in the design developmen
 t process in order to guarantee the development of correct designs. This i
 s called design synthesis. In this talk I will review 50 years of research
  on the synthesis problem\, describe the automata-theoretic approach devel
 oped to solve this problem\, and address current challenges. \n\n*Host:* B
 yron Cook - Microsoft Research Ltd
LOCATION:Small public lecture room\, Microsoft Research Ltd\, 7 J J Thomso
 n Avenue (Off Madingley Road)\, Cambridge
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