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SUMMARY:Tenstorrent - building AI/ML accelerators - Thaddeus Fortenberry\,
  Ali Ziadi and Luke Yen
DTSTART:20230801T090000Z
DTEND:20230801T110000Z
UID:TALK203623@talks.cam.ac.uk
CONTACT:Robert Mullins
DESCRIPTION:Tenstorrent build AI/ML hardware accelerators. This session wi
 ll contain three talks from their team:\n\n1. Thaddeus Fortenberry - RISC-
 V\, ASICs and Chiplets and the Future of Automotive: A Tenstorrent Perspec
 tive\n\nThaddeus Fortenberry’s presentation navigates the shifting lands
 cape of autonomous vehicles\, spotlighting advancements in next-generation
  infotainment and onboard networking.\nAt its core lies the RISC-V archite
 cture\, an open-source ISA heralding changes in automotive hardware.\n\n2.
  Ali Ziadi - Graph Native Accelerators for ML\n\nAli Zaidi will identify t
 he fundamental computational patterns prevalent in ML workloads and examin
 e how\nconventional systems encounter performance\, scaling\, and efficien
 cy bottlenecks when dealing with these patterns. Finally\, he will spotlig
 ht the key features of the Tensix AI\nArchitecture that address these chal
 lenges and lay the groundwork for a more future-proof roadmap of ML accele
 rators.\n\n3. Luke Yen - Scalable RISC-V Processors for AI\n\n \nLuke Yen
 ’s presentation will highlight our work on developing a disruptive serve
 r class RISC-V CPU architecture for AI\, data center packet processing\, a
 nd general-purpose compute. Our design is intended\nto be highly performan
 t\, matching the cutting edge of server-class CPUs in performance while be
 ing modular and scalable enough to create derivative designs that cater to
  a broad spectrum of price/performance design points for various markets a
 nd use cases. Luke will also highlight how we’re investing in chiplet te
 chnology to\nachieve modularity\, flexibility\, and performance scalabilit
 y in an era of slowing Moore’s Law gains.\n\n\n
LOCATION:LT2\, Computer Laboratory\, William Gates Building
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