BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Talks.cam//talks.cam.ac.uk// X-WR-CALNAME:Talks.cam BEGIN:VEVENT SUMMARY:Coherence Attacks and Defenses in 2.5D Integrated Systems - Profes sor Paul Gratz - Professor in the Department of Electrical and Computer En gineering\, Texas A&\;M University. Visiting academic at the Department of Computer Science and Technology\, University of Cambridge DTSTART:20231108T150500Z DTEND:20231108T155500Z UID:TALK204511@talks.cam.ac.uk CONTACT:Ben Karniely DESCRIPTION:Abstract: Industry is moving towards large-scale hardware syst ems which bundle processor cores\, memories\, accelerators\, etc. via 2.5D integration. These components are fabricated separately as chiplets and then integrated using an interconnect carrier\, i.e.\, an interposer. This new design style is beneficial in terms of yield and economies of scale\, as chiplets may come from various vendors and are relatively easy to inte grate into one larger sophisticated system. However\, the benefits of this approach come at the cost of new security and integrity challenges\, espe cially when integrating chiplets that come from not fully trusted\, third- party vendors.\n\nIn this talk\, I explore these challenges for modern int erposer-based systems of cache-coherent\, multi-core chiplets. First\, I w ill present a new form of coherence-oriented hardware Trojan attacks\, tha t pose a significant threat to chiplet-based designs and demonstrate how t hese basic attacks can be orchestrated to pose a significant threat to int erposer-based systems. Second\, I will show our proposal for a novel schem e using an active interposer as a generic\, secure-by-construction platfor m that forms a physical root of trust for modern 2.5D systems. The impleme ntation of our scheme is confined to the interposer\, resulting in little cost and leaving the chiplets and coherence system untouched. I will show that our scheme prevents a range of coherence attacks with low overheads on system performance\, ~4%. Overheads reduce as workloads increase\, ens uring the scheme's scalability.\n\n\nBio: Paul V. Gratz is a Professor in the department of Electrical and Computer Engineering at Texas A&M Univers ity. His research interests include efficient and reliable design in the context of high performance computer architecture\, processor memory syste ms and on-chip interconnection networks. He received his B.S. and M.S. de grees in Electrical Engineering from The University of Florida in 1994 and 1997 respectively. From 1997 to 2002 he was a design engineer with Intel Corporation. He received his Ph.D. degree in Electrical and Computer Eng ineering from the University of Texas at Austin in 2008. His paper\, "Syn chronized Progress in Interconnection Networks (SPIN) : A New Theory for D eadlock Freedom\," was selected as a Top Pick from the architecture confer ences in 2018 by IEEE Micro. His papers "Path Confidence based Lookahead P refetching" and "B-Fetch: Branch Prediction Directed Prefetching for Chip- Multiprocessors" were nominated for best papers at MICRO '16 and MICRO '14 respectively. At ASPLOS '09\, Dr. Gratz received a best paper award for "An Evaluation of the TRIPS Computer System." In 2016 he received the "Di stinguished Achievement Award in Teaching – College Level" from the Texa s A&M Association of Former Students and in 2017 he received the "Excellen ce Award in Teaching\, 2017" from the Texas A&M College of Engineering.\n\ n\nLink to join virtually: https://cam-ac-uk.zoom.us/j/81322468305\n\nA re cording of this talk is available at the following link: https://www.cl.ca m.ac.uk/seminars/wednesday/video/ LOCATION:Lecture Theatre 1\, Computer Laboratory\, William Gates Building END:VEVENT END:VCALENDAR