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SUMMARY:Massively Parallel Processor Array: an FPGA Replacement? - Prof Gu
 y Lemieux\, University of British Columbia
DTSTART:20091111T163000Z
DTEND:20091111T173000Z
UID:TALK21295@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:Work by David Grant\, Graeme Smecher\, Guy Lemieux (all UBC) a
 nd Rosemary Francis (UCambridge)\n\nFPGAs are incredibly flexible devices 
 that can behave as any digital\nlogic circuit\, subject to capacity and sp
 eed limits. But can a\nmassively parallel processor array (MPPA) behave li
 ke any digital\nlogic circuit as well?\n\nIn this talk\, we will consider 
 how to compile Verilog code for\nexecution in an MPPA. This is essentially
  a parallel logic simulation\nengine. By "running" several parallel proces
 ses\, the MPPA is\n"emulating" an FPGA. Yes\, this is a bit slower (1/10th
 )\, but there are\nsome remarkable advantages: CAD runtime or "compiling" 
 is 70x faster\,\nand you can time-multiplex logic resources. The latter fe
 ature is very\npowerful\, as you can trade space for execution time\, and 
 avoid the\nharsh capacity limits of traditional FPGAs. This could be used 
 to\nemulate much larger systems on a single MPPA than you can build on a\n
 single FPGA. Alternatively\, JIT-like compilation speeds and space/time\nf
 olding allows you to perform late binding of software to hardware\nfunctio
 ns. This also allows a single binary executable image to run at\ndifferent
  performance levels on different-sized MPPAs.\n\nThis is a practise talk f
 or an upcoming FPT2009 presentation.\n\nAbout the Speaker\n\nGuy Lemieux i
 s an Associate Professor at The University of British Columbia\,\nwhere he
  supervises a small group of students working on FPGA architecture\nand co
 mputing on FPGAs. Some of his recent contributions include bit-\nserial wi
 ring to alleviate bit-parallel datapath congestion\, a soft vector\nproces
 sor to accelerate embedded data-parallel tasks rather than\npainstakingly 
 crafting an RTL accelerator. Guy received 3 degrees at the\nUniversity of 
 Toronto under the supervision of Profs. David Lewis and\nStephen Brown.\n
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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