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SUMMARY:Enabling Efficient and Scalable DRAM Read Disturbance Mitigation v
 ia New Experimental Insights into Modern DRAM Chips / Methodologies\, Work
 loads\, and Tools for Processing-in-Memory: Enabling the Adoption of Data-
 Centric Architectures. - Giray Yağlıkçı / Geraldo Francisco
DTSTART:20240314T150000Z
DTEND:20240314T160000Z
UID:TALK213025@talks.cam.ac.uk
CONTACT:Ryan Gibb
DESCRIPTION:*Enabling Efficient and Scalable DRAM Read Disturbance Mitigat
 ion via New Experimental Insights into Modern DRAM Chips*\n\nDRAM is the p
 revalent main memory technology due to its high density and\nlow latency c
 haracteristics. The increasing need for faster access rates\nand larger DR
 AM capacity motivates improving the DRAM chip density.\nManufacturing tech
 nology node size shrinks over DRAM chip generations to\nprovide higher DRA
 M chip density. This technology scaling causes DRAM cell\nsize and cell-to
 -cell distance to reduce significantly. As a result\, DRAM\ncells become m
 ore vulnerable to read disturbance\, i.e.\, accessing a DRAM\ncell disturb
 s data stored in another physically nearby cell.\n\nTo provide a deeper un
 derstanding of and solutions to DRAM read\ndisturbance\, we 1) conduct exp
 erimental studies on real DRAM chips where we\ninvestigate the effects of 
 temperature\, access patterns\, intra-chip\nvariations\, and wordline volt
 age\; and 2) propose architecture-level\nsolutions to mitigate DRAM read d
 isturbance while it is exacerbated by\ntechnology node scaling and existin
 g mitigations face practicality\nchallenges due to a fundamental need for 
 exposing proprietary information.\nThis talk will provide a summary of the
 se works.\n\n_Bio:_\nGiray is a Ph.D. candidate in the Safari Research Gro
 up at ETH Zürich\,\nworking with Prof. Onur Mutlu. His current broader re
 search interests are\nin computer architecture\, systems\, and hardware se
 curity with a special\nfocus on DRAM robustness and performance. In partic
 ular\, his PhD research\nfocuses on understanding and solving DRAM read di
 sturbance vulnerability.\nGiray has published several works on this topic 
 in major venues such as\nHPCA\, MICRO\, ISCA\, DSN\, and SIGMETRICS. One o
 f these works\, BlockHammer\,\nwas named as a finalist by Intel in 2021 fo
 r the Intel Hardware Security\nAcademic Award. Giray's research is in part
  supported by Google and the\nMicrosoft Swiss Joint Research Center.\n\n*M
 ethodologies\, Workloads\, and Tools for Processing-in-Memory: Enabling th
 e Adoption of Data-Centric Architectures.*\n\nThe increasing prevalence an
 d growing size of data in modern applications\nhave led to high costs for 
 computation in traditional processor-centric\ncomputing systems. Moving la
 rge volumes of data between memory devices\n(e.g.\, DRAM) and computing el
 ements (e.g.\, CPUs\, GPUs) across\nbandwidth-limited memory channels can 
 consume more than 60% of the total\nenergy in modern systems. To mitigate 
 these costs\, the processing-in-memory\n(PIM) paradigm moves computation c
 loser to where the data resides\, reducing\n(and in some cases eliminating
 ) the need to move data between memory and\nthe processor. There are two m
 ain approaches to PIM: (1)\nprocessing-near-memory (PnM)\, where PIM logic
  is added to the same die as\nmemory or to the logic layer of 3D-stacked m
 emory\; and (2)\nprocessing-using-memory (PuM)\, which uses the operationa
 l principles of\nmemory cells to perform computation.\n\nMany works from a
 cademia and industry have shown the benefits of PnM and\nPuM for a wide ra
 nge of workloads from different domains. However\, fully\nadopting PIM in 
 commercial systems is still very challenging due to the\nlack of tools and
  system support for PIM architectures across the computer\narchitecture st
 ack\, which includes: (i) workload characterization\nmethodologies and ben
 chmark suites targeting PIM architectures\; (ii)\nframeworks that can faci
 litate the implementation of complex operations and\nalgorithms using the 
 underlying PIM primitives\; (iii) compiler support and\ncompiler optimizat
 ions targeting PIM architectures\; (iv) operating system\nsupport for PIM-
 aware virtual memory\, memory management\, data allocation\,\nand data map
 ping\; and (v) efficient data coherence and consistency\nmechanisms. Our g
 oal in this talk is to highlight tools and system support\nfor PnM and PuM
  architectures that aim to ease the adoption of PIM in\ncurrent and future
  systems.\n\n_Bio:_\nGeraldo F. Oliveira is a Ph.D. candidate in the Safar
 i Research\nGroup at ETH Zürich\, working with Prof. Onur Mutlu. His curr
 ent broader\nresearch interests are in computer architecture and systems\,
  focusing on\nmemory-centric architectures for high-performance and\nenerg
 y-efficient systems. In particular\, his Ph.D. research focuses on\ntaking
  advantage of new memory technologies to accelerate distinct classes\nof a
 pplications and provide system support for\nnovel memory-centric systems. 
 Geraldo has published several works on this\ntopic in major conferences an
 d journals such as HPCA\, ASPLOS\, ISCA\, MICRO\,\nand IEEE Micro.
LOCATION:FW26
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