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SUMMARY:Formal Verification of Analog and Mixed Signal Designs - Sofiene T
 ahar (Concordia University)
DTSTART:20100316T130000Z
DTEND:20100316T140000Z
UID:TALK23152@talks.cam.ac.uk
CONTACT:Thomas Tuerk
DESCRIPTION:Analog and mixed signal (AMS) designs are integrated circuits 
 required at the interfaces of a system-on-chip or embedded system with the
  physical environment. The verification of AMS designs is concerned with t
 he assurance of correct functionality\, in addition to checking robustness
  with respect to different types of inaccuracies like parameter tolerances
 \, nonlinearities\, etc. In this talk\, I will review recent research on t
 he\napplication of formal methods to the verification of AMS designs and p
 resent some successful approaches based on techniques such as Model Checki
 ng\, Constraint based verification\, Run-time verification\, Assertion bas
 ed verification\, and Automated Theorem Proving. These approaches handle c
 ontinuous as well as discrete-time AMS designs with both linear and non-li
 near behaviors. To illustrate the effectiveness of above techniques\,\nI w
 ill use as case studies several examples of analog and mixed signal system
 s\, like oscillator circuits\, switched capacitor based designs\, Delta-Si
 gma modulators\, PLLs\, etc.\n\n\n*BIO:*\nSofiene Tahar is Professor in th
 e Department of Electrical and Computer Engineering at Concordia Universit
 y\, Montreal\, Quebec\, Canada. He received\nhis PhD in Computer Science i
 n 1994 from the University of Karlsruhe and his Diploma in Computer Engine
 ering in 1990 from the University of Darmstadt. Prof. Tahar has made contr
 ibutions and published papers in the\nareas of formal hardware verificatio
 n\, microprocessor and system-on-chip verification\, analog and mixed sign
 al circuits verification\, VLSI design automation\, and formal probabilist
 ic\, statistical and reliability analysis of systems. Prof. Tahar is found
 er and director of the Hardware Verification Group (http://hvg.ece.concord
 ia.ca).
LOCATION:Computer Laboratory\, William Gates Building\, Room SS03
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