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SUMMARY:Shorter Cycles\, Better Chips: Compiler Infrastructure for Acceler
 ating the Hardware-Software Design Loop - Moritz Scherer
DTSTART:20260122T130000Z
DTEND:20260122T140000Z
UID:TALK243514@talks.cam.ac.uk
CONTACT:Tobias Grosser
DESCRIPTION:As compute systems become increasingly heterogeneous and speci
 alized\, compiler infrastructure is no longer just a way to generate code
 —it can be a practical tool to shape hardware design decisions\, tighten
  end-to-end design cycles\, and share the verification burden. \n\nFrom th
 e perspective of a silicon startup building custom acceleration\, this tal
 k highlights opportunities that emerge when we treat compilation as a cros
 s-cutting system: using compiler-driven feedback to connect RTL and archit
 ectural choices to the software stack and real workloads early enough to m
 atter. \n\nWe will discuss how this broader view enables faster iteration 
 through tighter hardware–software feedback loops\, and how lowering work
 load descriptions into kernels\, schedules\, and data movement strategies 
 can better exploit heterogeneous hardware. \n\nFinally\, we touch on how c
 ompiler-driven infrastructure can turn workloads and generated programs in
 to systematic test vehicles—helping expose corner cases and improving co
 nfidence in correctness as both hardware and software evolve.\n\n\nBio:\nM
 oritz Scherer is the CTO of Mosaic SoC AG\, where he leads the development
  of ultra-low-power embedded AI and computer vision hardware and the assoc
 iated hardware–software stack\, targeting AR/VR\, robotics\, and always-
 on edge intelligence. \n\nHe earned his PhD at ETH Zürich in Luca Benini
 ’s group\, focusing on embedded heterogeneous acceleration and compiler 
 toolchains for efficient deployment on resource-constrained systems. His w
 ork centers on full-stack co-design\, bridging workload descriptions to ef
 ficient execution on specialized compute platforms.\n
LOCATION:Computer Laboratory\, SS03
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