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SUMMARY:Seamless Clock Synchronization under Migration - Darryl Veitch (Un
 iversity of Melbourne)
DTSTART:20100617T150000Z
DTEND:20100617T160000Z
UID:TALK25251@talks.cam.ac.uk
CONTACT:Eiko Yoneki
DESCRIPTION:I will describe recent work on a new timekeeping architecture 
 for virtualized systems\, in the context of Xen. Built upon a feed-forward
  based RADclock synchronization algorithm\, it ensures that the clocks in 
 each OS sharing the hardware derive from a single central clock in a resou
 rce effective way\, and that this clock is both accurate and robust. A key
  advantage is simple\, seamless migration with consistent time.  We also p
 rovide a detailed examination of the HPET and Xen Clocksource counters. Al
 l results are validated using a careful methodology in a hardware supporte
 d testbed.\n\nBio: Darryl Veitch completed a BSc.~Hons.~at Monash Universi
 ty\, Australia (1985)\nand a mathematics Ph.D.~from DAMPT\, Cambridge (199
 0). He worked  at\nTRL (Telstra\, Melbourne)\, CNET (France Telecom\, Pari
 s)\, KTH\n(Stockholm)\, INRIA (Sophia Antipolis\, France)\, Bellcore (New 
 Jersey)\, RMIT (Melbourne) and EMUlab and CUBIN at The University of\nMelb
 ourne\, where he is a Principal Research Fellow. \nHe is currently on sabb
 atical with INRIA and Technicolor in Paris\, France.\nHis research interes
 ts are in computer networking and include traffic modelling\, parameter es
 timation\, active measurement\, traffic sampling\, and clock synchronisati
 on over networks.  He is a Fellow of the IEEE.\n
LOCATION:FW26\, Computer Laboratory\, William Gates Builiding
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