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SUMMARY:Post-Silicon Validation:  New Frontiers for Formal Verification Re
 search - Alan Hu\, University of British Columbia
DTSTART:20100721T100000Z
DTEND:20100721T110000Z
UID:TALK25457@talks.cam.ac.uk
CONTACT:Microsoft Research Cambridge Talks Admins
DESCRIPTION:*Abstract:* Post-silicon validation is the problem of determin
 ing whether a new design\, as fabricated in silicon\, behaves according to
  its specification.  As such\, post-silicon validation shares attributes w
 ith pre-silicon design verification (which seeks to find bugs in the desig
 n before it has been fabricated)\, as well as manufacturing test (which se
 eks to find manufacturing defects during high-volume production of chips).
   Post-silicon validation currently consumes a large fraction of the total
  verification schedule on typical large designs\, and the problem is growi
 ng worse.  Even worse\, the schedule variability is greatest post-silicon\
 , creating unacceptable uncertainty in time-to-market.\n\nThe post-silicon
  validation problem has unique features and challenges that create new que
 stions and problems for formal verification research.  In this talk\, I wi
 ll survey the problem space\, present a bit more depth on some recent work
  applying formal techniques to post-silicon validation\, and suggest some 
 areas where I believe formal techniques hold great promise.\n\n*Biography:
 * Alan J. Hu received his BS and PhD degrees from Stanford University.\nHe
  is a Professor and former Associate Head in the Computer Science Departme
 nt at the University of British Columbia.  For 20 years\, his main researc
 h focus has been automated\, practical techniques for formal verification.
   He has served on the program committees of all major CAD and formal veri
 fication conferences\, and chaired or co-chaired CAV (1998)\, HLDVT (2003)
 \, FMCAD (2004)\, and HVC (2008). He was also a Technical Working Group Ke
 y Contributor on the 2001 International Technology Roadmap for Semiconduct
 ors\, and is a member of the Technical Advisory Board of Jasper Design Aut
 omation.\n
LOCATION:Small public lecture room\, Microsoft Research Ltd\, 7 J J Thomso
 n Avenue (Off Madingley Road)\, Cambridge
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