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SUMMARY:Multi-Target Data-Parallel Programming with Accelerator for GPUs\,
  Multicore Processors and FPGAs - Satnam Singh\, Microsoft Research Cambri
 dge
DTSTART:20101006T131500Z
DTEND:20101006T141500Z
UID:TALK26384@talks.cam.ac.uk
CONTACT:Stephen Clark
DESCRIPTION:In this presentation I will introduce the motivate the need fo
 r data-parallel\ndescriptions that can be automatically re-targeted to exe
 cute on wildly\ndifferent kinds of hardware including vector instructions 
 on multicore\nprocessors\, GPUs (graphics cards) and FPGAs (special circui
 ts that can be\nquickly reconfigured to implement new functionality). Spec
 ifically\, I shall\ntalk about the Accelerator project at Microsoft which 
 has produced a library of\ndata-parallel operations and memory transformat
 ions that aim to be high level\nenough to permit civilian programmers to e
 xpress their algorithms in a manner\nwhich can be automatically compiled t
 o parallel implementations on GPUs\, SSE3\nvector instructions on multiple
  cores and Xilinx FPGA circuits. As the\nprocessing capabilities on our de
 sktops\, on our devices and in the cloud become\nmore heterogeneous we wil
 l increasingly need programming models that allow us\nto compile to multip
 le targets from a single description.  Although this seems\nvery hard to d
 o in the general case we do believe there is a good chance of\nsolving thi
 s problem for a class of data-parallel algorithms.\n\nSatnam Singh's resea
 rch interests include involves finding novel ways to program and use recon
 figurable chips called FPGAs and in parallel functional programming. Satna
 m Singh completed his PhD at the University of Glasgow in 1991 where he de
 vised a new way to program and analyze digital circuits described in a spe
 cial functional programming language. He then went on to be an academic at
  the same university and lead several research projects that explored nove
 l ways to exploit FPGA technology for applications like software radio\, i
 mage processing and high resolution digital printing\, and graphics. In 19
 98 he moved to San Jose California to join Xilinx's research lab where he 
 developed a language called Lava in conjunction with Chalmers University w
 hich allows circuits to be laid out nicely on chips to give high performan
 ce and better utilization of silicon resources. In 2004 he joined Microsof
 t in Redmond Washington where we worked on a variety of techniques for pro
 ducing concurrent and parallel programs and in particular explored join pa
 tterns and software transactional memory. In 2006 he moved to Microsoft's 
 research laboratory in Cambridge where he works on reconfigurable computin
 g and parallel functional programming. He is a fellow of the IET and a vis
 iting professor at Imperial College and a visiting lecturer at Chalmers in
  Gothenburg\, Sweden.
LOCATION:Lecture Theatre 1\, Computer Laboratory
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