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SUMMARY:The RLOC is Dead -- Long Live the RLOC - Satnam Singh\, Microsoft 
 Research Cambridge
DTSTART:20101123T110000Z
DTEND:20101123T120000Z
UID:TALK28085@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:Are user specified layout constraints of significant value any
 more? Certainly in the past the use of the RLOC layout constraint for Xili
 nx FPGAs was essential for achieving the best possible performance for man
 y kinds of highly structured designs. However\, have CAD tools evolved to 
 the point where they can always compute layouts as good as (if not better 
 than) humans? Or has the introduction of on-chip hard cores\, which create
  an irregular 2D surface for layouts\, made layout specification impractic
 al? Or has the varying pitch and types of combinational logic blocks (CLBs
 ) made it intractable to produce layout descriptions that are portable acr
 oss architectures? We show that the use of layout constraints still delive
 rs a large performance gain for Xilinx's recent Virtex-6 family of FPGAs. 
 The performance gain is sometime large enough to accommodate a reduction o
 f two speed grades.\n
LOCATION:SC04\, Computer Laboratory\, William Gates Building
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