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SUMMARY:Implementation of ISE for the micro-threaded model in LEON3 SPARC 
 - Dr Martin Danek\, UTIA Prague
DTSTART:20110628T100000Z
DTEND:20110628T113000Z
UID:TALK31716@talks.cam.ac.uk
CONTACT:Prof Simon Moore
DESCRIPTION:The talk will describe instruction set extensions for a\nvaria
 nt of multi-threading called micro-threading for the LEON3 SPARCv8\nproces
 sor. An architecture of the developed processor will be presented\nand its
  key blocks described - cache controller\, register file\, thread\nschedul
 er. The processor has been implemented in a Xilinx Virtex2Pro and\nVirtex5
  FPGAs. The extensions will be evaluated in terms of extra\nresources need
 ed\, and the overall performance of the developed processor\nwill be shown
  for a simple DSP computation typical for embedded systems.\n\nBio: Martin
  Danek received his PhD from the Czech Technical University\nin Prague in 
 2004\, where he researched physical design algorithms for\nFPGAs. During h
 is PhD he spent one year at the ICSC\, UWE Bristol\nstudying emergent beha
 viours in distributed multi-agent systems. After\njoining UTIA in 2003 he 
 focused on tools and methods for using of\npartial runtime reconfiguration
  in FPGAs. Recently he has become\ninterested in efficient architectures w
 ith pipelined functional units\nand their implementations in FPGAs\, and i
 n methods that increase the\nlevel of abstraction in digital design.\n
LOCATION:Lecture Theatre 2\, Computer Laboratory\, William Gates Building
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