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SUMMARY:Scale-Out Processors - Boris Grot\, EPFL
DTSTART:20120921T090000Z
DTEND:20120921T100000Z
UID:TALK39858@talks.cam.ac.uk
CONTACT:Microsoft Research Cambridge Talks Admins
DESCRIPTION:A growing number of today’s most relevant applications are s
 erved online and run in large-scale datacenters characterized by thousands
  of servers and multi-megawatt power budgets. As Dennard scaling comes to 
 a halt\, experts are projecting exponential growth in datacenter power and
  performance requirements in the coming decade\, driven by the rising popu
 larity of the online service model. To efficiently meet the computing need
 s in the post-Dennard era\, datacenters will rely on a new form of ISA –
  Integration\, Specialization\, and Approximation.\n \nAs a first step tow
 ard this post-Dennard ISA\, we have developed Scale-Out Processors – a p
 rocessor design methodology that maximizes performance per TCO on scale-ou
 t workloads running in large-scale datacenters. Using a metric of performa
 nce density\, our methodology facilitates the design of optimal configurat
 ions\, called pods\, of core\, cache\, and interconnect building blocks. E
 ach pod is a stand-alone server-on-chip\, a feature that avoids the expens
 e and complexity of global (i.e.\, inter-pod) interconnect and coherence s
 upport. As I will show\, Scale-Out Processors enable higher performance\, 
 lower TCO\, and better technology scalability over existing design alterna
 tives.
LOCATION:Large lecture theatre\, Microsoft Research Ltd\, 7 J J Thomson Av
 enue (Off Madingley Road)\, Cambridge
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