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SUMMARY:On the efficient implementation of large round-robin arbiters - Em
 anuel Savin (Intel)
DTSTART:20130418T090000Z
DTEND:20130418T100000Z
UID:TALK44557@talks.cam.ac.uk
CONTACT:Eiko Yoneki
DESCRIPTION:This talk describes a binary-tree search architecture for roun
 d-robin arbiters (RRA)\, suitable for efficient implementations of resourc
 e schedulers for L2/L3 switch ASICs. The RRA architecture comprises two ma
 in components: 1) a priority-select block\, which consists of a tree of OR
 -gates selecting maximum values across various segments of the binary-requ
 est vector\, and 2) a grant-select module\, which employs a unit-weighted 
 representation of the priority index. The proposed design is compared with
  a conventional crossbar fabric arbiter used in the Tiny Terra project\, a
 nd shown to provide significant improvements on both latency as well as ga
 te-counts. The gate-count improvement is achieved by sharing the same gran
 t-select module for two priority-encoder units\, while the overall delays 
 are reduced through the use of a united-weighted priority index. A possibl
 e extension of the proposed architecture to the implementation of arbiters
  with selection mechanisms designed to extract a 2nd (or n-th) highest pri
 ority active request\, is also suggested.\n \nBio: C. Emanuel Savin is a s
 taff engineer with Intel Corp.\, in Swindon. He has a Ph.D. degree from Co
 ncordia University in Montreal\, Canada\, and his field of interest is in 
 the area of hardware architectures for router components and signal proces
 sing applications\, and the related implementation methodologies targeting
  ASICs and FPGAs.\n
LOCATION:FW11\, Computer Laboratory
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