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SUMMARY:Hardware Neural Network Accelerators - Olivier Temam\, Inria
DTSTART:20131205T140000Z
DTEND:20131205T150000Z
UID:TALK49238@talks.cam.ac.uk
CONTACT:Microsoft Research Cambridge Talks Admins
DESCRIPTION:As architectures evolve towards heterogeneous multi-cores comp
 osed of a mix of cores and accelerators\, designing accelerators which rea
 lize the best possible tradeoff between flexibility and efficiency is beco
 ming a prominent issue. The first question is for which category of applic
 ations one should primarily design accelerators ? Together with the archit
 ecture trend towards accelerators\, a second simultaneous and significant 
 trend in high-performance and embedded applications is developing: many of
  the emerging high-performance and embedded applications rely on machine-l
 earning techniques. This trend in application comes together with a third 
 and equally remarkable trend in machine-learning where a small number of t
 echniques\, based on neural networks\, have been proved in the past few ye
 ars to be state-of-the-art across a broad range of applications. As a resu
 lt\, there is a unique opportunity to design accelerators which can realiz
 e the best of both worlds: significant application scope together with hig
 h performance and efficiency due to the limited number of target algorithm
 s. Moreover\, the inherent robustness of neural networks can be leveraged 
 to design accelerators which are also tolerant to defects and transient fa
 ults. \nI will discuss the opportunity to integrate such accelerators in c
 omputing systems\, present several accelerators we have designed in the pa
 st few years\, and the performance\, energy and fault-tolerance benefits t
 hey can bring.
LOCATION:Auditorium\, Microsoft Research Ltd\, 21 Station Road\, Cambridge
 \, CB1 2FB
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