BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Talks.cam//talks.cam.ac.uk//
X-WR-CALNAME:Talks.cam
BEGIN:VEVENT
SUMMARY:NetOS Talklet - Reinoud Elhorst
DTSTART:20140401T120000Z
DTEND:20140401T130000Z
UID:TALK51825@talks.cam.ac.uk
CONTACT:Ionel Gog
DESCRIPTION:C/C++11 introduced a memory model and explicit orderings on at
 omic variables into the C/C++ languages. This allows developers of multith
 readed programs on multicore systems to choose between a sequentially cons
 istent or more relaxed memory model\, with the former easier to reason abo
 ut and the latter giving faster programs on modern architectures.\n\nLLVM 
 IR incorporated a C/C++11 compatible memory model in LLVM 3.0.  ARM is the
  most widespread LLVM-supported architecture with a weak memory model by d
 efault\, and explicit barriers are provided by the data memory barrier (dm
 b) instruction.  We have found that that LLVM's insertion of memory barrie
 rs is too aggressive in certain cases and present two machine instruction 
 passes that remove these extra instructions where they can be proven to be
  redundant.  The result is a 40% speedup in the lockless data structure th
 at we profiled.  We compare the sequentially consistent implementation wit
 h one that makes use of more relaxed acquire and release barriers and demo
 nstrate that the compiler is able to generate the same machine code for bo
 th.\n\nThis talk will cover the memory model in C/C++11\, LLVM IR\, and on
  the hardware and discuss the importance of efficient generation of relaxe
 d memory semantics for scalable multithreaded code.  We will present our o
 ptimisations and propose future directions for improving LLVM's code gener
 ation on weakly ordered architectures.
LOCATION:Computer Laboratory\, William Gates Building\, Room FW11
END:VEVENT
END:VCALENDAR