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SUMMARY:Towards Zero Latency Photonic Switching - Dr Philip Watss\, UCL
DTSTART:20140828T100000Z
DTEND:20140828T110000Z
UID:TALK53296@talks.cam.ac.uk
CONTACT:Microsoft Research Cambridge Talks Admins
DESCRIPTION:Developments in silicon photonics could see photonic network e
 lements co-packaged with processors creating low energy networks-on-chip (
 NoC) or direct links between processors across a data centre.   However\, 
 although it is easy to show that basic photonic network elements have lowe
 r latency and energy requirements than their electronic counterparts\, on 
 the system level the issue is not so clear cut.  For example\, the schedul
 ing overhead incurred in reconfiguring photonic switches can be a signific
 ant overhead for the short messages created by shared memory networks and 
 Ethernet.  Furthermore\, recent NoC results have suggested that the edge b
 uffering required in photonic networks results in greater overall energy c
 onsumption than electronic NoCs.  Due to the fundamental differences betwe
 en electronic and photonic networks\, new architectures and scheduling alg
 orithms are required to exploit photonics in future systems.  This talk wi
 ll describe low energy\, low latency network architectures for two scenari
 os: (1) a shared memory coherence network for cache coherent multicore chi
 ps or multi-socket servers\; (2) an optical top-of-rack switch for data ce
 ntres.
LOCATION:Auditorium\, Microsoft Research Ltd\, 21 Station Road\, Cambridge
 \, CB1 2FB
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