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SUMMARY:Authenticated Encryption\, The CAESAR Project\, and a SoC Crypto P
 eripheral - Dr. Markku-Juhani O. Saarinen ERCIM Research Fellow Norwegian 
 University of Science and Technology\, Trondheim
DTSTART:20140808T150000Z
DTEND:20140808T154500Z
UID:TALK53690@talks.cam.ac.uk
CONTACT:Robert Watson
DESCRIPTION:During 2014 I've been involved with the U.S. NIST-funded CAESA
 R\nproject (Competition for Authenticated Encryption: Security\,\nApplicab
 ility\, and Robustness). This project seeks to find secure\nalternatives t
 o the Advanced Encryption Standard (AES) and more\nspecifically its GCM Au
 thenticated Encryption mode\, which is currently\nthe only option in NSA's
  unclassified COTS "Suite B"\, certified up to\nTop Secret. I've broken a 
 couple of CAESAR proposals and B. Minaud of\nFrench ANSSI broke my other\,
  lightweight proposal\; I will give an\noverview of current status of this
  project.\n\nMy remaining CAESAR first round candidate STRIBOB / WHIRLBOB 
 is based\non the Russian 2012 GOST hash standard "Streebog" and the ISO ha
 sh\nstandard Whirlpool. I show how to modify the fundamental cryptographic
 \ntransformation of these hashes into a Sponge-based Authenticated\nEncryp
 tion algorithm while maintaining a provable security link to the\noriginal
  well-studied algorithms. I'll describe how a Whirlpool / AES\n- like MDS 
 structure was uncovered from the GOST standard\nspecification. I've met wi
 th the Russian designers of Streebog and the\nupcoming Russian Encryption 
 Standard "Kuznyechik" in Moscow in June\n2014. I will present some general
  observations on their cryptographic\ndesign strategies and recent Russian
  crypto policies in general.\n\nI've also been building a WHIRLBOB impleme
 ntation as an on-chip\nperipheral that sits on the AXI bus of ARM based So
 Cs. Such a target\nmakes sense as it is absolutely dominant in mobile phon
 es\, tablets\,\nand IoT devices. These are not only the most common comput
 ing and\ncommunication devices in 2014\, but also most in need of power an
 d\nperformance optimization. I will demonstrate an implementation based\no
 n Xilinx Zynq platform\, which is dual-core Cortex A9 SoC with Artix 7\nFP
 GA Logic Fabric for peripherals (on the same chip).
LOCATION:Computer Laboratory\, William Gates Building\, Room FW11
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