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SUMMARY:Software-driven ISA Design: How software requirements drove the ev
 olution of the CHERI instruction set. - David Chisnall
DTSTART:20141008T120000Z
DTEND:20141008T130000Z
UID:TALK55217@talks.cam.ac.uk
CONTACT:Peter Sewell
DESCRIPTION:\nThe version of the Capability Hardware Enhanced RISC Instruc
 tions (CHERI) architecture presented at ISCA this year was the second majo
 r revision of the CHERI ISA\, adding a capability oriented memory protecti
 on model to a conventional RISC (MIPS R4K-compatible) base instruction set
 .  CHERI was always intended to provide hardware-enforced security for sof
 tware that forms part of trusted computing base\, which is typically writt
 en in C or C++.  These languages have an abstract model that allows implem
 entations that provide strict memory protection but also have large bodies
  of legacy code (crucially\, the code that could most benefit from improve
 d security) that were not written with language-enforced memory safety in 
 mind.\n\nThe CHERI ISA underwent significant refinements as we added capab
 ility support to the Clang front end for LLVM and CHERI ISA support to the
  back end.  It is now undergoing further refinement\, leading to a third i
 teration of the instruction set\, as we try to compile large bodies of sof
 tware targeting CHERI.  This talk will discuss the lessons learned at each
  step and the importance of evaluating computer architecture research with
  real-world software.
LOCATION:FW11
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