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SUMMARY:Reversing chip design for hardware security characterization  - Fr
 anck Courbon\, Security group\, University of Cambridge
DTSTART:20161129T140000Z
DTEND:20161129T150000Z
UID:TALK69404@talks.cam.ac.uk
CONTACT:Laurent Simon
DESCRIPTION:*Abstract*:\nIn a more and more connected world\, attacks targ
 et different payment\, identification and transportation systems leading t
 o various economic\, social and societal impacts. Some of those attacks ar
 e directly based on embedded systems hardware structure. Thus\, among othe
 rs\, attacks can profit from transistors' behavior or can aim to modify so
 me part of an integrated circuit. Problematics behind Hardware Trojan dete
 ction\, fault attacks and memory cell content extraction are addressed. Ba
 sed on a 3 steps methodology\, Sample preparation - Scanning Electron Micr
 oscopy (SEM) - Image processing\, we depict how interesting Scanning Elect
 ron Microscopy intrinsic features are for hardware security. On one hand\,
  after a frontside preparation down to transistors' active region\, the me
 thodology allows detecting malicious hardware modification\, extracting me
 mory contents from a type of ROM or locating individual transistors prior 
 to a fault attack in a chip's synthesized logic. On the other hand\, after
  a backside preparation down to transistors' tunnel oxides\, the methodolo
 gy allows retrieving Flash/EEPROM memory contents. The methodology is depi
 cted with the help of practical experiments. We will particularly point ou
 t the cost\, speed and efficiency advantages for such SEM based approaches
 . \n\n*Bio*:\nFranck Courbon is a Post-Doctoral Research Associate in the 
 Computer Laboratory Security team. He is currently working on integrated c
 ircuit memory contents extraction. He previously worked for Gemalto\, wher
 e he has been awarded of a PhD. in partnership with the Ecole des Mines of
  Saint-Etienne in France. 
LOCATION:LT2\, Computer Laboratory\, William Gates Building
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