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SUMMARY:Genus\, Numerics and Architectural Level Optimisation - Theo Drane
 \, Cadence Design Systems
DTSTART:20170127T140000Z
DTEND:20170127T150000Z
UID:TALK70240@talks.cam.ac.uk
CONTACT:Dominic Mulligan
DESCRIPTION:** NOTE NON-STANDARD ROOM**\n\nA crucial component of Cadence'
 s logic synthesis solution Genus is that that focuses on the synthesis of 
 arithmetic operators. The synthesis of a cluster of the fundamental operat
 ors that is power efficient\, small\, fast and can be successfully placed 
 and routed is the persistent challenge and drives innovation.\n\nGenus als
 o provides a library of IP components\, ChipWare\, for all the essential c
 hip building blocks (floating-point operations\, transcendental functions\
 , FIFOs\, arbiters...). These are highly parameterisable\, have to be func
 tionally correct and highly optimised. Simulation based verification techn
 iques are powerless in providing any real functional confidence for such c
 omponents. Formal techniques are thus the main focus of ChipWare verificat
 ion.\n\nBut we don't just learn to get it right\, we also learn how to get
  it wrong. Certain applications (DSP\, vision processing\, GPU) are error 
 tolerant. This freedom could be used to provide hardware improvements by u
 sing ideas from approximate computing.\n\nWe also explore higher level syn
 thesis for various number formats and the error analysis associated with C
 hipWare usage\, particularly floating-point.\n\nThis talk will hint and me
 ander through the myriad of associated research challenges. The landscape 
 that Genus operates in draws us into close collaboration with other Cadenc
 e divisions (Logical Equivalence Checking - Conformal LEC\, Model Checking
  - Jasper and High Level Synthesis - Stratus) as well as customers from th
 e entire application space (GPU\, CPU\, DSP...).\n\n*Bio*: Dr. Theo Drane 
 started his career working for the Datapath consultancy Arithmatica in 200
 2 after completely a Mathematics degree from the University of Cambridge. 
 He moved to Imagination Technologies in 2005 where his interests were data
 path optimisation\, verification and validation. After a two year sabbatic
 al to work for an independent financial data provider\, Markit\, he return
 ed to Imagination to head up their Datapath group while studying for a PhD
  in conjunction with Imperial College London’s Electrical and Electronic
  Engineering Department. He now leads the architectural optimization group
  for the Genus Synthesis solution in Cadence Design Systems\, whose R&D is
  based in Byron House\, Cambridge Business Park\, San Jose & Noida.
LOCATION:FW11
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