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SUMMARY:The Next-Generation Vector Architecture for HPC - Mbou Eyole\, ARM
DTSTART:20170130T140500Z
DTEND:20170130T145500Z
UID:TALK70317@talks.cam.ac.uk
CONTACT:Alastair Beresford
DESCRIPTION:ARM’s next-generation vector architecture known as the Scala
 ble Vector Extension (SVE) has been created primarily for energy-efficient
  high-performance computing (HPC) designs. SVE has emerged as a key ingred
 ient in the race towards Exascale computing and has features aimed at meet
 ing the ever-increasing computing demands of scientific research in domain
 s such as meteorology\, astronomy\, quantum physics\, and fluid dynamics.\
 n\nIn this presentation\, I will go through the design of the SVE architec
 ture\, from the set of design requirements and constraints to various inst
 ruction set components. I will explain why a Vector-Length-Agnostic approa
 ch was adopted in the design of the architecture and how it works in pract
 ice. I will also explain results obtained from measuring the performance o
 f critical kernels taken from standard HPC benchmark suites\, and highligh
 t any scalability issues that were encountered.\n\n\nBio: Mbou Eyole is a 
 processor research engineer at ARM. He is responsible for creating next-ge
 neration architectures and has been a key contributor to ARM’s new vecto
 r architecture called the Scalable Vector Extension. He is a Chartered Eng
 ineer and has filed over 14 patents on CPU architectures\, instruction set
  extensions\, and microarchitectures. His research focuses on improving th
 e applicability of SIMD architectures to a broader range of workloads whic
 h have high computational demands. In particular\, he wrestles with the pr
 oblem of irregular computation pathways and non-affine memory accesses in 
 parallel workloads. He also has significant experience in sensor network d
 esign and in his PhD (University of Cambridge\, 2008) he proposed a multi-
 layered decentralised model of distributed computation with energy-efficie
 nt multicore nodes managing sub-clusters of sensor nodes. Before joining A
 RM\, he was a Research Fellow at Trinity College\, Cambridge\, where he in
 vestigated scheduling in massively parallel architectures.
LOCATION:SS03\, Computer Laboratory\, William Gates Building
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