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SUMMARY:Crossing the Architectural Barrier: Evaluating Representative Regi
 ons of Parallel HPC Applications - Roxana Rusitoru\, ARM
DTSTART:20170525T120000Z
DTEND:20170525T130000Z
UID:TALK71313@talks.cam.ac.uk
CONTACT:Ekaterina Kochmar
DESCRIPTION:Exascale computing will get mankind closer to solving importan
 t social\, scientific and engineering problems. Due to high prototyping co
 sts\, High Performance Computing (HPC) system architects make use of simul
 ation models for design space exploration and hardware-software co-design.
  However\, as HPC systems reach exascale proportions\, the cost of simulat
 ion increases\, since simulators themselves are largely single-threaded. T
 ools for selecting representative parts of parallel applications to reduce
  running costs are widespread\, e.g.\, BarrierPoint achieves this by analy
 sing\, in simulation\, abstract characteristics such as basic blocks and r
 euse distances. However\, architectures new to HPC have a limited set of t
 ools available.\n\nIn this work\, we provide an independent cross-architec
 tural evaluation on real hardware—across Intel and ARM—of the BarrierP
 oint methodology\, when applied to parallel HPC proxy applications. We pre
 sent both cases: when the methodology can be applied and when it cannot. I
 n the former case\, results show that we can predict the performance of fu
 ll application execution by running shorter representative sections. In th
 e latter case\, we dive into the underlying issues and suggest improvement
 s. We demonstrate a total simulation time reduction of up to 178x\, whilst
  keeping the error below 2.3% for both cycles and instructions.
LOCATION:Computer Laboratory\, William Gates Building\, Room FW26
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