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SUMMARY:P4-NetFPGA - Stephen Ibanez (Stanford University)
DTSTART:20170420T140000Z
DTEND:20170420T150000Z
UID:TALK71968@talks.cam.ac.uk
CONTACT:Liang Wang
DESCRIPTION:Today\, P4 is the leading high level programming language for 
 expressing how packets are processed by the data-plane of any programmable
  packet processing device. There have already been many new and exciting a
 pplications proposed at top networking conferences\, such as SIGCOMM\, whi
 ch take advantage of data-plane programmability. Unfortunately\, it has be
 en a significant challenge for researchers to test their P4 programs in re
 al hardware at line-rate. In this talk\, I will introduce the P4-NetFPGA w
 orkflow\, which uses the Xilinx P4-SDNet toolchain and is designed to make
  it easy for researchers to compile their P4 programs to the NetFPGA SUME 
 board\, thus facilitating hardware testing. NetFPGA is an open platform en
 abling researchers and instructors to build high-speed\, hardware-accelera
 ted networking systems and is the de-facto experimental platform for line-
 rate implementations of network research. I will conclude with a discussio
 n about the future research direction for the P4-NetFPGA workflow.\n\nBio:
 \nStephen Ibanez is a PhD Candidate at Stanford working with Professor Nic
 k McKeown. His research interests involve finding new and exciting applica
 tions for programmable data-planes\, running P4 programs on programmable h
 ardware\, network measurement and management\, as well as network security
 . He has experience using P4 to design switches that implement proactive c
 ongestion control algorithms for next generation datacenter networks. Step
 hen is leading the effort to bring together a community of developers and 
 users for the P4-NetFPGA platform. He has performed demos at SIGCOMM as we
 ll as at numerous P4 Workshops.
LOCATION:FW26\, Computer Laboratory\, William Gates Building
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