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Memory and Datapath optimisation for FPGA co-processors

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If you have a question about this talk, please contact Dr George A Constantinides .

The available memory bandwidth often forms the bottleneck in performance when using FPG As as hardware co-processors. As a result, when considering high level synthesis for FPG As, it is important to optimise the datapath and the supporting memory subsystem in parallel so that performance can be maximised. This talk presents an overview for such a co-optimisation process, based around loop pipelining, and its application to a sample benchmark.

This talk is part of the CAS FPGA Talks series.

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