Accelerating Iterative Methods Using FPGAs

Antonio Roldao (PhD@IC)

Tuesday 07 October 2008, 14:00-15:00

If you have a question about this talk, please contact Dr George A Constantinides .

This talk will discuss the quantification of how much different mantissa/exponent bit-widths impact FPGA resource utilization.

We will look at how these data, in conjunction with acceptable error bounds in iterative methods, can be used to accelerate the solution of linear systems.

This talk is part of the CAS FPGA Talks series.

Accelerating Iterative Methods Using FPGAs

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👤 Speaker: Antonio Roldao (PhD@IC)
📅 Date & Time: Tuesday 07 October 2008, 14:00 - 15:00
📍 Venue: Mahanakorn Laboratory, EEE

Questions? Contact Dr George A Constantinides

Abstract

This talk will discuss the quantification of how much different mantissa/exponent bit-widths impact FPGA resource utilization.

We will look at how these data, in conjunction with acceptable error bounds in iterative methods, can be used to accelerate the solution of linear systems.

Series This talk is part of the CAS FPGA Talks series.

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