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CG: Optimizing FPGA Speed using Custom Precision

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If you have a question about this talk, please contact Dr George A Constantinides .

With the continuing exploration of accelerating iterative methods on FPG As, in this upcoming seminar, I will present the latest results obtained from analyzing the speed-up of an FPGA vs a CPU (in double precision) by reducing the word-length.

I will also show a plot of the different number of iterations obtained from performing every sum reduction (of the CG method) sequentially or in a tree, for the current MPC Citation Model Aircraft testbench.

In addition, I will show and request feedback on a preliminary poster on for the banded implementation paper that is to be presented at FPT ’08.

This talk is part of the CAS FPGA Talks series.

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Large Seminar Room, 1st floor, Institute of Public Health, Forvie Site, Cambridge BioMedical Campus, CB2 0SR Hybrid: in-person in Cambridge & online via Teams MR13, CMS Pavilion E

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