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Improving Real-time Observability in Embedded Logic Analysis

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  • UserNicola Nicolici (McMaster University, Canada)
  • ClockFriday 07 November 2008, 16:00-17:00
  • HouseRoom 611, EEE.

If you have a question about this talk, please contact Dr George A Constantinides .

To identify design errors that escape pre-silicon verification, post-silicon validation is becoming an important step in the implementation flow of digital integrated circuits and systems. Embedded logic analysis has emerged as a complementary technique to scan chains for improving real-time observability during in-system validation. In this talk we discuss some recent research for improving real-time observability in embedded logic analysis.

This talk is part of the CAS FPGA Talks series.

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