Abstract

Electronic Design Automation (EDA) tools enable development of next generation semiconductor devices. Through advances in manufacturing techniques, feature size has plummeted enabling logic density and design complexity to rocket. Development machines have gone many-core and distributed processing has become commonplace, yet many design optimization algorithms are unable to scale to exploit the compute power available. A new approach to optimization is needed!

In this talk, we will cover some of the history of EDA to provide an insight into the scope and scale of modern design optimization. We will learn how machine learning techniques can be applied to some of the problems facing EDA , and consider some of the developments explored as part of our internship program at Cadence.

Biography: Andrew Hall gained his BSc Computer Science from UCL and has since amassed more than 20 years of EDA experience. He has developed a simulated annealing placement engine and soft processors for Field Programmable Gate Arrays (FPGAs) at Altera and is currently a software architect for high performance and low power Clock Tree Synthesis (CTS) at Cadence Design Systems.