Abstract

Are user specified layout constraints of significant value anymore? Certainly in the past the use of the RLOC layout constraint for Xilinx FPG As was essential for achieving the best possible performance for many kinds of highly structured designs. However, have CAD tools evolved to the point where they can always compute layouts as good as (if not better than) humans? Or has the introduction of on-chip hard cores, which create an irregular 2D surface for layouts, made layout specification impractical? Or has the varying pitch and types of combinational logic blocks (CLBs) made it intractable to produce layout descriptions that are portable across architectures? We show that the use of layout constraints still delivers a large performance gain for Xilinx’s recent Virtex-6 family of FPG As. The performance gain is sometime large enough to accommodate a reduction of two speed grades.